The present invention relates generally to integrated circuit design, and more particularly to integration of power delivery network design and digital logic design flows.
Digital logic circuitry for integrated circuits are often designed using a number of design tools, with operation of the tools being arranged in a sequence, which may considered to provide a digital logic design flow. Very often, these design flows include specifying digital circuit operations, for example using a hardware description language (HDL) such as Verilog or VHDL, creating a register transfer level (RTL) description of the circuit based on the HDL, synthesizing the RTL description to a netlist, and using a place and route tool to determine placement of gates of the netlist and routing of signals between the gates. In addition, generally various testing schemes are applied at each stage of the process, generally to determine if each stage is formally equivalent to a prior stage, and steps of the process may be repeated depending on the outcome of the tests.
The digital logic design flow is generally effective at reducing costs for design of integrated circuitry, and for providing integrated circuit designs that meet functional requirements.
Some portions of semiconductor ICs, however, are generally designed outside of the digital logic design flow. For example, power distribution network (PDN) circuitry, including on-chip voltage regulators and associated circuitry, are generally specialized circuits that are specially handled in the design process, and not incorporated into the digital logic design flow. Instead, the PDN may be specially designed and specially placed, which may result in inconsistencies or undesired effects.